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VHDL IMPLEMENTATION OF VEDIC
MATHEMATICAL SUTRAS
Vadiraj Sagar*, Shripad Sagar, Sudhindracharya, Vedavyas Mathad, Subhash Kulkarni
Department of Electronics and Communication Engineering
Poojya Doddappa Appa College of Engg., Gulbarga – 585 102 Karnataka, India
Email: {Sagar.Vadiraj, Shripad_sagar}@rediffmail.com, sudhee_j4u@yahoo.com,
{vedavyasmathad, subhashsk}@gmail.com
ABSTRACT:
The “Time” and “area” are the two important constraints in any processor IC design. In any digital design process, these two constraints play a contradictory role and thus there exists a trade-off between with them. Optimizing the two said constraints is a challenging task in the design process.
Vedic mathematics comes with the sim
plest and effective algorithms for solving any typical engineering problem. This has motivated to develop a mathematical system standing on the pillars of the “Vedic” principles. Two of the Vedic mathematical sutras, generalized multiplication sutra and squaring sutra, have been optimally designed at simulation level using VHDL. The results are found to be encouraging with the usage of port mapping concept. The design architectures of these sutras promise a long way in bringing out an efficient (in terms of cell usage & delay) arithmetic unit for the future generation processors.
KEYWORDS:
Urdhva-Tiryagbhyam, Dvandva-Yoga, VHDL simulation.

1. Introduction
The very word ‘Veda’ has the derivational meaning i.e. the fountainhead and illimitable storehouse of all knowledge. Vedic mathematics is the name given to the ancient system of mathematics or, to be precise a unique technique of calculations based on simple rules and principles with which many mathematical problems can be solved, be it arithmetic, algebra, geometry or trigonometry. The system is based on 16 Vedic sutras or aphorisms, which are actually word formulae describing natural ways of solving a whole range of mathematical problems [1].
Conventional mathematics is an integral part of engineering education since most engineering system designs are based on various mathematical approaches. All the leading manufacturers of microprocessors owe their architectures to the conventional binary arithmetic. The Vedic mathematics approach is totally different and considered very close to the way a human mind works [2]
Perhaps the most striking feature of the Vedic systems is its coherence. Instead of unrelated combinational technique, the whole system is beautifully interleaved and unified. e.g.: It is easily reversed to allow one-line division and a simple squaring method can be reversed to give one line square roots. This unifying quality makes mathematics easy and enjoyable and encourages innovation.
In the present work two generalized sutras, viz, urdhva-tiryagbhyam and dvandva yoga for multiplication and squaring operations respectively are implemented in an efficient way. The work emphasizes the hierarchical approach used to develop the higher-level digital systems using the lower level systems as a component in it. The concept of “port map” available in the VHDL literature is intelligently exploited in developing the appropriate digital systems.
2. Urdhva – Tiryagbhyam sutra for multiplication
Urdhva–tiryagbhyam is the general formula applicable to all cases of multiplication. The formula being very short and terse consists of only one compound word and means “vertically and crosswise”. The application of this sutra will ensure simpler means to solve typical multiplication problems encountered in the engineering environment.
A simple example will suffice to clarify the operation of the urdhva-tiryagbhaym
Suppose we have to multiply 12 by 13
(i) We multiply the most significant digit 1 of multiplicand vertically by most significant digit 1 of the multiplier, get their product 1 and set it down as the most significant part of the answer
(ii) We then multiply 1 and 3, and 1 and 2 crosswise, add the two, get 5 as the sum and set it down as the middle part of the answer and
(iii) We multiply 2 and 3 vertically, get 6 as their product and put it down as the last the right hand most part of the answer.
Thus 12 x 13 = 156. It bears a simple extendible form in a similar way for multidigit multiplication [1].
This process of ascent and a descent going forward with the digits on the upper row and coming crossway with the digits on the lower row. If this principle of ordinary algebraic multiplication is properly understood and carefully applied to the arithmetical multiplication on hand, the urdhva-tiryak sutra may be deemed to have been successfully mastered in the actual practice[1].
3. Dvandva Yoga for squaring
In order to calculate the square of a number, ’duplex’ property has been proposed. In the duplex, we take twice the product of the outermost pair, and so on till no pairs are left [4]. When there are odd numbers of bits in the original sequence there is one digit left by itself in the middle, and this is taken care as below
For a 1 digit number, D is square of the number i.e., D (a)=a^2;
For a two digit number D is twice as their product, D (ab)=2*a*b;
For a three-digit number D is twice the product of the outer pair and square of the middle digit. D (abc)=2*a*c+b^2;
For a four digit number D is twice the product of the outer pair plus twice the product of the inner pair, i.e D (abcd)=2*a*d+2*b*c
4. Implementation of the Vedic algorithms
In this study, the algorithms are implemented on VHDL and logic simulations are done on Model Simulator. The Synthesis is done using Xilinx Web Pack 6.3. After Gate level synthesis from High level behavioral and/or the structural RTL VHDL codes, basic schematics are optimized. The designs are optimized for Speed and Area, using Xilinx, Device Family: Vertex E, Device xcv 300e, Package BG432, Speed grade of –8. The device is made up of multiplexers and LUTs.[3]
Initially, the low level designs for 8 bit processing were derived out of VHDL codes, which were made to ape Vedic algorithms. The codes were highly optimized to the level of implementation. The underlying algorithms were framed in such a way that they maintained one to one relationship with the Vedic algorithms available in the literature. Thus, in case of urdhva tiryagbhyam method, the algorithm begin with multiplication of lower most bits of the two multiplication operands and end up with the same operation on their respective most significant bits.
Also, in dvandva yoga method of squaring for 8 bit processing, the algorithm started off manipulating the duplex of least significant bit of the 8 bit operand and ended up on most significant bit
The codes developed for 8 bit processing proved to be enough reliable and flexible to be extended to any higher level processing but they failed to promise the necessary optimization of the targeted design constraints, which was the penultimate aim of the project. There was no any regular relationship amongst the values of the design constraints.
Thus, in order to limit the design constraint values, the concept of “port map” was invoked. The concept facilitated the instantiation of the low level 8 bit modules and rearranging them to develop its immediate higher version ie.for the development of 16-bit system. Port map concept helped to on the bricks of 8 bit systems. Similarly, 32 bit systems were developed on 16 bit systems and so on.
It was again the feature of symmetry of Vedic sutras, which helped to sort out the problem of optimization of design constraints, and made easy, the exploitation of port map concept
The higher systems were developed from the previous obtained lower level 8-bit systems using the concept of port map. Thus, in case of multiplication, all the designed systems followed the same architecture as shown in the figure 1. The depicted architecture for multiplication houses three adders and four instances of lower level multiplier components, i.e., one 16-bit multiplier architecture involves three adders and four 8-bit multiplier components. This trend follows for any higher-level systems.
Eg: in urdhva tiryag bhyam method
If “AB” and “CD” are two 16-bit operand to be multiplied then according to the sutra the process should begin with
’B’*’D’ which is multiplication of two 8 bit operands. For this to happen, the digital model developed for 8-bit multiplication operation was used.
Similarly, the same model could be instantiated to implement the following operations
A*D, B*C and A*C
Thus, one could see “4” instantiations of 8 bit multiplication modules in 16 bit multiplication system and added to that there is also a 16 bit addition operation which is indicated as (A*D)+(B*C) which made use of 16 bit addition module.
Two more addition modules were incorporated to facilitate the addition of the carry byte produced in the previous process
Thus the architecture of 16 bit multiplication is an arrangement of “4” 8 bit multiplication modules and “3” 16 bit adders. Thus as shown in figure 1 the port map helped to retain the regularity of the architecture. The concept was also worked upon the squaring system as shown in figure 2.
5. Experimental Results and Discussion.
Port map concept available in the VHDL literature [5,6] was exploited to make possible, the implementation of the designs in efficient way. The concept of port map abridges the low level design modules with the higher ones without the loss of generality involved in the design process.
Thus the systems developed, can be readily expanded to any higher levels without reflecting any abrupt changes in the values of design constraints as it is evident in the case of 16 bit systems developed by 8-bit systems and so on.
The proposed techniques of square computation and multiplication will be highly beneficial due to its regular structure. The proposed architecture can be easily laid out on silicon and can work at high speed. It has the advantage that as the number of bit increases its gate delay and area increases comparatively at a slower rate than conventional algorithms [2,3].
Multiplier Type
Speed
Grade
Cell
Use
Estimated
Delay(ns)
8×8
Bit
-8
224
13.174
Conven –
Tional
16×16
Bit
-8
916
16.380
8×8
Bit
-8
16
7.385
Proposed
Vedic
Approach
16×16
Bit
-8
149
14.031
Table 1: Comparison of conventional methods with the proposed Urdhva Tiryag Bhyam method for multiplication (Vendor – Xilinx, Device & family – VirtexE Xcv300e, Package – Bg432)
The time and the area are the two targeted constraints. The area constraint necessarily depicts the amount of area consumed by the system in terms of “”cell usage” and the time constraints speaks of the maximum combinational path delay encountered in the system. The designs were built so effectively that they promise the necessary optimization required for the practical implementations. Typical comparison has been shown below in Table 1 and 2 summarizing the essence and the effectiveness of the Vedic procedures. The proposed Vedic method for multiplication was compared with the traditional method of multiplications in terms of area and time constraints and the proposed squaring designs were compared with the respective systems developed on the basis of Flynn’s algorithms and that proposed by Thapliyal and others [2,3,4].
Multiplier Type
Speed
Grade
Cell
Use
Estimated
Delay(ns)
8×8
Bit
-8
42
13.516
Proposed
Squaring
Method
16×16
Bit
-8
127
17.815
8×8
Bit
-8
190
15.193
Proposed
Square by
Thapliyal
Et. al.
16×16
Bit
-8
751
23.600
8×8
Bit
-8
177
30.370
Square
Proposed
By Flynn
Et. al.
16×16
Bit
-8
727
60.646
Table 2: Comparison of the Proposed Squaring system constraints with the system constraints developed by Thapliyal et.al. and Flynn et. Al. (Vendor – Xilinx, Device & family – VirtexE Xcv300e, Package – Bg432)
6. Conclusions:
It’s quite evident that digital systems constructed upon the Vedic principles serves as a better choice in sufficing various design constraints. The implementation of these models can be made with the help of suitable adaptive architectures supporting the underlying Vedic principles. The hierarchical approach treated in the context was the interesting part of the process.
The effective implementation of these sutras can be made possible with the support of suitable architectures, which can be brought up by the VLSI technologies available in the literature [2].
VLSI technology can provide the necessary design and simulation tools to develop processor based on BCD architecture. Such processors would be the most suitable for implementing Vedic algorithms and may further offer savings in processing
References
[1] Jagadguru Swami Sri Bharati Krsna Tirthaji Maharaja, Vedic mathematics, (Motilal Banarsidass Publishers Pvt Ltd, Delhi 2001).
[2] P Chidgupkar and M T Karad, Implementation of Vedic Algorithms in DSP, Global Jl. of Engng. Educ., vol 8, no 2,published in Australia 2004 UICEE.
[5] Douglas L. Perry, VHDL, (3 edition, Mc Graw-Hill. 1999).
[3] H. Thapliyal and M .B Srinivas, Novel Time -Area Power efficient single floating-point multiplier, MAPLD 2005/1011
[6] J. Bhaskar, A VHDL Primer, (Pearson Education.3 Edition.2005)
[4] H.Thapliyal and M.B Srinivas, A high speed and efficient method of elliptic curve encryption, MAPLD 2005/1013
Figure 1: Proposed architecture for N bit multiplication
Figure 2: Proposed architecture for N bit squaring