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The “Time” and “area” are the two important constraints in any processor IC design. In any digital design process, these two constraints play a contradictory role and thus there exists a trade-off between with them. Optimizing the two said constraints is a challenging task in the design process.
Vedic mathematics comes with the sim
plest and effective algorithms for solving any typical engineering problem. This has motivated to develop a mathematical system standing on the pillars of the “Vedic” principles. Two of the Vedic mathematical sutras, generalized multiplication sutra and squaring sutra, have been optimally designed at simulation level using VHDL. The results are found to be encouraging with the usage of port mapping concept. The design architectures of these sutras promise a long way in bringing out an efficient (in terms of cell usage & delay) arithmetic unit for the future generation processors.

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