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MULTIPLICATION ALGORITHM STRUCTURE ABSTRACT
Jul 30th, 2007 by admin
MULTIPLICATION ALGORITHM STRUCTURE
ABSTRACT
This paper presents a comprehensive evaluation of the different multiplication algorithms and parallel multiplier structures for the design of scalable multiplication units to be incorporated into hardware components. Traditional Arithmetic Logic Units of digital computers and Application Specific Integrated Circuits have had to deal with more than one, different data representation formats. Arithmetic processes use fixed length small bit multipliers while cryptographic applications and graphics applications use wide bit multipliers. Selection of multipliers for a particular application involves comparison of accuracy, speed , area, power and scalability. We implemented the algorithmic and structural based multipliers using VHDL in FPGAs and the observations give a comprehensive idea for selection.
1. Introduction
Multiplication is one of the most vital functions in many processor applications. Various structures and logic have been proposed for implementation of multipliers, which has made their use in complex applications like cryptography. Though typical multipliers implemented for arithmetic purposes are of 8,16,32,even 64 bit wide, cryptography demands an even larger width, typically 512 or 1024 bits. So scalability becomes an important feature for the design. Algorithmic implementation of multipliers is scalable to a good extent, while they suffer a longer delay. Structure based array implementations are faster while scalability increases design complexity as well as expense. Moreover, multipliers occupy large area, have long latency and consume considerable power. [1],[2],Therefore, multipliers which offer either of the following design targets -scalability, reconfigurability, high speed, low power consumption, regularity of layout and hence less area or even a combination of some of these features in one multiplier are required thereby making them suitable for various VLSI implementations.[3]
(Note: This Paper was presented in ICSIP Please Download the paper for proper formatting, images and symbols)
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