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And this time we are again back!!! with a bang. The Software Freedom Week 08 will be celebrated from 14th Sept 2008 t0 20th Sept 2008. Team BVBCET(www.bvb.edu) takes immense pleasure to Host this mega open source promo event in this part of Karnataka.

Software Freedom Day (softwarefreedomday.org ), which is globally declared on 20th Sept 2008, will be celebrated as a Software Freedom Week in BVBCET. The event aims at

1) Promotion of the spirit of OpenSource.

2) Provide a competitive platform for the students of this part of Karnataka so that they can explore and exhibit their technical caliber and update their knowledge of the present contemporary technologies.

Please visit this portal for more updates.

1 st Workshop on Overview and Architecture of ULTRA Sparc T2 Processor

OpenSparc Workshop in BVBCET was an event to trigger the minds of Hardware Engineers towards OpenSource concept of processor designing, It was the first of its kind in this part of Karnataka

It was a marathon workshop for 6 Hours extensively covering important aspects of the UltraSPARC T2 Processor.
Photo Gallery

Date conducted: 23rd Feb 2008 (Saturday)

Timings: 11 to 1 PM, 1.30 to 3.30 PM 4.00 to 6.00 PM

Institutes participated: BVBCET Hubli (29 students)

                                 SDMCET Hubli (15 students)

                                 P.C.Jabin College BCA (5 students)

                                 M.C.A BVBCET (12 students)

Total Attendance:  61 Students from E&C,IT,E&E,CS,IS,BCA & MCA Branches

Resource Person: Mr Nasim Hussain from SUN

Nasim stunned the audience by his expertise and blissful presentation, we felt that we were in some TED Conference!, rather than presenting he inspired the audience and he delivered an eye opener and awakened us to realize the mammoth lag of our curriculum compared to the industrial race.

The Workshop aimed at presenting various improvisations made over the old mode of processor designing, and an overview and architecture of the UltraSPARC T2 processor was presented.

Project ideas for the students interested in this sector were also presented. The presentation included only 277 slides!!

We are planning to have the next version of this workshop which will provide hands on experience on how to

Break into the Verilog Source code of UltraSPARC T2

Flirt with the source code.

Compiling and Building the code

Contributing/Adding our own module to the source

RTL Verification

We are working on arranging the resources (Machines with Solaris loaded, Cadence Tools installed) for this upcoming event.

Download Slides of Presentation

Thanking you,

Karthik Kulkarni

Campus Ambassador

SUN Microsystems

BVBCET Hubli

Email: kartik.kulkarni@sun.com

VHDL IMPLEMENTATION OF VEDIC
MATHEMATICAL SUTRAS
Vadiraj Sagar*, Shripad Sagar, Sudhindracharya, Vedavyas Mathad, Subhash Kulkarni
Department of Electronics and Communication Engineering
Poojya Doddappa Appa College of Engg., Gulbarga – 585 102 Karnataka, India
Email: {Sagar.Vadiraj, Shripad_sagar}@rediffmail.com, sudhee_j4u@yahoo.com,
{vedavyasmathad, subhashsk}@gmail.com
ABSTRACT:
The “Time” and “area” are the two important constraints in any processor IC design. In any digital design process, these two constraints play a contradictory role and thus there exists a trade-off between with them. Optimizing the two said constraints is a challenging task in the design process.
Vedic mathematics comes with the sim
plest and effective algorithms for solving any typical engineering problem. This has motivated to develop a mathematical system standing on the pillars of the “Vedic” principles. Two of the Vedic mathematical sutras, generalized multiplication sutra and squaring sutra, have been optimally designed at simulation level using VHDL. The results are found to be encouraging with the usage of port mapping concept. The design architectures of these sutras promise a long way in bringing out an efficient (in terms of cell usage & delay) arithmetic unit for the future generation processors.
KEYWORDS:
Urdhva-Tiryagbhyam, Dvandva-Yoga, VHDL simulation.

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